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Information about the I-Boom deployment operation during the LEOP.


General

Purpose & Objectives

Prepare the I-Boom deployement RPW-related operations during the LEOP.

Working Group Members

RPW sub-system teams will also contribute to define the RPW modes to be set during the deployement.

Operation preparation

Context & assumptions

RPW will be switched-off during the LEOP, except during the Boom and ANT deployments operations.

During the Boom deployement the MAG instrument will be also switched-on.

The SSMM will be available.

Overall timeline


I-BOOM deployment: Launch and Early Orbit Phase (LEOP)

 

RPW OPERATIONS PLAN

Launch configuration

RPW OFF. Antennas are stowed. I-Boom with SCM is stowed.

 


 

 

I-Boom deplOYMENT timeline


  1. RPW MEB and SCM preamplifier switch on
  2. Beginning of the BOOM deployment
  3. End of the BOOM deployment
  4. RPW switch off

 

 

 

In this phase, RPW measures the noise of the platform. RPW is set in a specific configuration for I-BOOM deployment. Measurements will be taken during the first and last 10 minutes (before and after the IBOOM deployment). RPW in BURST mode with both spectral modes (all frequencies for B) and waveforms.

Minimal requirements:

  • THR: B field on channel 1 and E on channel 2 (all frequencies, max freq resolution).
  • LFR: spectral mode maximum frequency resolution.
  • No TDS.

Maximal requirements

  • THR: B field on channel 1 and E on channel 2 (all frequencies).
  • LFR: spectral mode maximum frequency resolution, B waveforms at 256 Hz.
  • TDS snapshots

Parameters for RPW configuration

We require RPW subsystems to provide TC parameters (engineering value) for the configuration during  the I-BOOM deployment.

 

TDS

 

TC_TDS_LOAD_COMMON_PAR

Value

TC_TDS_LOAD_NORMAL_PAR

Value

 

 

 

 

      CP_TDS_C_HF_LF_POWER

 

TC_TDS_LOAD_NORMAL_PAR

 

 SY_TDS_C_LF_MUX_RESERVED

 

   SY_TDS_N_SAMP_RATE_RESERVED

 

      CP_TDS_C_LF_MUX_CONF_SET

 

      CP_TDS_N_SAMP_RATE

 

SY_TDS_C_LFINMUX_RESERVED2

 

      SY_TDS_N_RS_RESERVED

 

 SY_TDS_C_LFINMUX_RESERVED

 

      SY_TDS_N_RS_ENAB

 

      SY_TDS_C_ENAB_LF_IN6

 

      CP_TDS_N_RS_ADC_CH_NR

 

      SY_TDS_C_ENAB_LF_IN5

 

      SY_TDS_N_RS_ADC_CH4

 

      SY_TDS_C_ENAB_LF_IN4

 

      SY_TDS_N_RS_ADC_CH3

 

      SY_TDS_C_ENAB_LF_IN3

 

      SY_TDS_N_RS_ADC_CH2

 

      SY_TDS_C_ENAB_LF_IN2

 

      SY_TDS_N_RS_ADC_CH1

 

      SY_TDS_C_ENAB_LF_IN1

 

      SY_TDS_N_HF_RESERVED

 

      SY_TDS_C_HF_RESERVED

 

      SY_TDS_N_AD4_HF2_LOAD

 

      SY_TDS_C_AD4_HF2_LOAD

 

      SY_TDS_N_AD3_HF2_LOAD

 

      SY_TDS_C_AD3_HF2_LOAD

 

      SY_TDS_N_AD2_HF1_LOAD

 

      SY_TDS_C_AD2_HF1_LOAD

 

      SY_TDS_N_AD1_HF3_LOAD

 

      SY_TDS_C_AD1_HF3_LOAD

 

      SY_TDS_N_HF_CH4_LOW_GAIN

 

      SY_TDS_C_HF_CH4_LOW_GAIN

 

    SY_TDS_N_HF_CH4_INPUT_ENAB

 

SY_TDS_C_HF_CH4_INPUT_ENAB

 

      SY_TDS_N_HF_CH3_LOW_GAIN

 

      SY_TDS_C_HF_CH3_LOW_GAIN

 

    SY_TDS_N_HF_CH3_INPUT_ENAB

 

SY_TDS_C_HF_CH3_INPUT_ENAB

 

      SY_TDS_N_HF_CH2_LOW_GAIN

 

      SY_TDS_C_HF_CH2_LOW_GAIN

 

   SY_TDS_N_HF_CH2_INPUT_ENAB

 

 SY_TDS_C_HF_CH2_INPUT_ENAB

 

      SY_TDS_N_HF_CH1_LOW_GAIN

 

      SY_TDS_C_HF_CH1_LOW_GAIN

 

   SY_TDS_N_HF_CH1_INPUT_ENAB

 

 SY_TDS_C_HF_CH1_INPUT_ENAB

 

      SY_TDS_N_AD4_MUXA_SET

 

      SY_TDS_C_AD4_MUXA_SET

 

      SY_TDS_N_AD4_MUXA_INH

 

      SY_TDS_C_AD4_MUXA_INH

 

      SY_TDS_N_AD4_MUXB_SET

 

      SY_TDS_C_AD4_MUXB_SET

 

      SY_TDS_N_AD4_MUXB_INH

 

      SY_TDS_C_AD4_MUXB_INH

 

      SY_TDS_N_AD3_MUXA_SET

 

      SY_TDS_C_AD3_MUXA_SET

 

      SY_TDS_N_AD3_MUXA_INH

 

      SY_TDS_C_AD3_MUXA_INH

 

      SY_TDS_N_AD3_MUXB_SET

 

      SY_TDS_C_AD3_MUXB_SET

 

      SY_TDS_N_AD3_MUXB_INH

 

      SY_TDS_C_AD3_MUXB_INH

 

      SY_TDS_N_AD2_MUXA_SET

 

      SY_TDS_C_AD2_MUXA_SET

 

      SY_TDS_N_AD2_MUXA_INH

 

      SY_TDS_C_AD2_MUXA_INH

 

      SY_TDS_N_AD2_MUXB_SET

 

      SY_TDS_C_AD2_MUXB_SET

 

      SY_TDS_N_AD2_MUXB_INH

 

      SY_TDS_C_AD2_MUXB_INH

 

      SY_TDS_N_AD1_MUXA_SET

 

      SY_TDS_C_AD1_MUXA_SET

 

      SY_TDS_N_AD1_MUXA_INH

 

      SY_TDS_C_AD1_MUXA_INH

 

      SY_TDS_N_AD1_MUXB_SET

 

      SY_TDS_C_AD1_MUXB_SET

 

      SY_TDS_N_AD1_MUXB_INH

 

      SY_TDS_C_AD1_MUXB_INH

 

      SY_TDS_N_RS_DELAY_COARSE

 

      SY_TDS_C_CACHE_CTRL

 

      SY_TDS_N_RS_DELAY_FINE

 

SY_TDS_C_DISABLE_TIME_SYNC

 

      SY_TDS_N_RS_LEN

 

      SY_TDS_C_SW_CONF_WORD2

 

      SY_TDS_N_FILTERS

 

      SY_TDS_C_SW_CONF_WORD3

 

      SY_TDS_N_TS_RESERVED

 

 

 

      SY_TDS_N_TS_ENAB

 

 

 

      CP_TDS_N_TS_ADC_CH_NR

 

 

 

      SY_TDS_N_TS_ADC_CH4

 

 

 

      SY_TDS_N_TS_ADC_CH3

 

 

 

      SY_TDS_N_TS_ADC_CH2

 

 

 

      SY_TDS_N_TS_ADC_CH1

 

 

 

      SY_TDS_N_TS_PERIOD_COARSE

 

 

 

      SY_TDS_N_TS_PERIOD_FINE

 

 

 

      SY_TDS_N_TS_LEN

 

 

 

      SY_TDS_N_QUEUE_LEN

 

 

 

      SY_TDS_N_STAT_DATA_PERIOD

 

 

 

      SY_TDS_N_1D_HIST_PERIOD

 

 

 

      SY_TDS_N_2D_HIST_PERIOD

 

 

 

      CP_TDS_N_STAT_DATA

 

 

 

      SY_TDS_N_MAMP_ENAB

 

 

 

      SY_TDS_N_MAMP_DEC_RATE

 

 

 

      SY_TDS_N_MAMP_ADC_CH4

 

 

 

      SY_TDS_N_MAMP_ADC_CH3

 

 

 

      SY_TDS_N_MAMP_ADC_CH2

 

 

 

      SY_TDS_N_MAMP_ADC_CH1

 

 

 

      CP_TDS_N_1D_HIST1_TYPE

 

 

 

      CP_TDS_N_1D_HIST1_AXIS

 

 

 

      CP_TDS_N_1D_HIST2_TYPE

 

 

 

      CP_TDS_N_1D_HIST2_AXIS

 

 

 

      CP_TDS_N_1D_HIST3_TYPE

 

 

 

      CP_TDS_N_1D_HIST3_AXIS

 

 

 

      CP_TDS_N_1D_HIST4_TYPE

 

 

 

      CP_TDS_N_1D_HIST4_AXIS

 

 

 

      CP_TDS_N_2D_HIST1_TYPE

 

 

 

      CP_TDS_N_2D_HIST1_X_AXIS

 

 

 

      CP_TDS_N_2D_HIST1_Y_AXIS

 

 

 

      CP_TDS_N_2D_HIST2_TYPE

 

 

 

      CP_TDS_N_2D_HIST2_X_AXIS

 

 

 

      CP_TDS_N_2D_HIST2_Y_AXIS

 

 

 

SY_TDS_N_STAT_PAR_THRESHOLD

 

 

 

      CP_TDS_ALGO_SELECTION

 

 

 

      SY_TDS_ALGO_DUST_NUM

 

 

 

      SY_TDS_ALGO_MIN_QUALITY

 

 

 

      SY_TDS_ALGO_CHANNEL

 

 

 

      SY_TDS_ALGO_STAT_ADC4

 

 

 

      SY_TDS_ALGO_STAT_ADC3

 

 

 

      SY_TDS_ALGO_STAT_ADC2

 

 

 

      SY_TDS_ALGO_STAT_ADC1

 

 

 

      SY_TDS_ALGO_MIN_AMP

 

 

 

      SY_TDS_ALGO_THRESH_WAVE

 

 

 

      SY_TDS_ALGO_THRESH_DUST

 

 

 

      SY_TDS_ALGO_THRESH_EX

 

 

 

      SY_TDS_ALGO_PARAM1

 

 

 

      SY_TDS_ALGO_PARAM2

 

 

 

TC_TDS_LOAD_NORMAL_PAR

 

 

 

SY_TDS_N_SAMP_RATE_RESERVED

 

 

 

      CP_TDS_N_SAMP_RATE

 

 

 

      SY_TDS_N_RS_RESERVED

 

 

 

      SY_TDS_N_RS_ENAB

 

 

 

      CP_TDS_N_RS_ADC_CH_NR

 

 

 

      SY_TDS_N_RS_ADC_CH4

 

 

 

      SY_TDS_N_RS_ADC_CH3

 

 

 

      SY_TDS_N_RS_ADC_CH2

 

 

 

      SY_TDS_N_RS_ADC_CH1

 

 

 

      SY_TDS_N_HF_RESERVED

 

 

 

      SY_TDS_N_AD4_HF2_LOAD

 

 

 

      SY_TDS_N_AD3_HF2_LOAD

 

 

 

      SY_TDS_N_AD2_HF1_LOAD

 

 

 

      SY_TDS_N_AD1_HF3_LOAD

 

 

 

      SY_TDS_N_HF_CH4_LOW_GAIN

 

 

 

    SY_TDS_N_HF_CH4_INPUT_ENAB

 

 

 

      SY_TDS_N_HF_CH3_LOW_GAIN

 

 

 

    SY_TDS_N_HF_CH3_INPUT_ENAB

 

 

 

      SY_TDS_N_HF_CH2_LOW_GAIN

 

 

 

   SY_TDS_N_HF_CH2_INPUT_ENAB

 

 

 

      SY_TDS_N_HF_CH1_LOW_GAIN

 

 

 

    SY_TDS_N_HF_CH1_INPUT_ENAB

 

 

 

      SY_TDS_N_AD4_MUXA_SET

 

 

 

      SY_TDS_N_AD4_MUXA_INH

 

 

 

      SY_TDS_N_AD4_MUXB_SET

 

 

 

      SY_TDS_N_AD4_MUXB_INH

 

 

 

      SY_TDS_N_AD3_MUXA_SET

 

 

 

      SY_TDS_N_AD3_MUXA_INH

 

 

 

      SY_TDS_N_AD3_MUXB_SET

 

 

 

      SY_TDS_N_AD3_MUXB_INH

 

 

 

      SY_TDS_N_AD2_MUXA_SET

 

 

 

      SY_TDS_N_AD2_MUXA_INH

 

 

 

      SY_TDS_N_AD2_MUXB_SET

 

 

 

      SY_TDS_N_AD2_MUXB_INH

 

 

 

      SY_TDS_N_AD1_MUXA_SET

 

 

 

      SY_TDS_N_AD1_MUXA_INH

 

 

 

      SY_TDS_N_AD1_MUXB_SET

 

 

 

      SY_TDS_N_AD1_MUXB_INH

 

 

 

      SY_TDS_N_RS_DELAY_COARSE

 

 

 

      SY_TDS_N_RS_DELAY_FINE

 

 

 

      SY_TDS_N_RS_LEN

 

 

 

      SY_TDS_N_FILTERS

 

 

 

      SY_TDS_N_TS_RESERVED

 

 

 

      SY_TDS_N_TS_ENAB

 

 

 

      CP_TDS_N_TS_ADC_CH_NR

 

 

 

      SY_TDS_N_TS_ADC_CH4

 

 

 

      SY_TDS_N_TS_ADC_CH3

 

 

 

      SY_TDS_N_TS_ADC_CH2

 

 

 

      SY_TDS_N_TS_ADC_CH1

 

 

 

      SY_TDS_N_TS_PERIOD_COARSE

 

 

 

      SY_TDS_N_TS_PERIOD_FINE

 

 

 

      SY_TDS_N_TS_LEN

 

 

 

      SY_TDS_N_QUEUE_LEN

 

 

 

      SY_TDS_N_STAT_DATA_PERIOD

 

 

 

      SY_TDS_N_1D_HIST_PERIOD

 

 

 

      SY_TDS_N_2D_HIST_PERIOD

 

 

 

      CP_TDS_N_STAT_DATA

 

 

 

      SY_TDS_N_MAMP_ENAB

 

 

 

      SY_TDS_N_MAMP_DEC_RATE

 

 

 

      SY_TDS_N_MAMP_ADC_CH4

 

 

 

      SY_TDS_N_MAMP_ADC_CH3

 

 

 

      SY_TDS_N_MAMP_ADC_CH2

 

 

 

      SY_TDS_N_MAMP_ADC_CH1

 

 

 

      CP_TDS_N_1D_HIST1_TYPE

 

 

 

      CP_TDS_N_1D_HIST1_AXIS

 

 

 

      CP_TDS_N_1D_HIST2_TYPE

 

 

 

      CP_TDS_N_1D_HIST2_AXIS

 

 

 

      CP_TDS_N_1D_HIST3_TYPE

 

 

 

      CP_TDS_N_1D_HIST3_AXIS

 

 

 

      CP_TDS_N_1D_HIST4_TYPE

 

 

 

      CP_TDS_N_1D_HIST4_AXIS

 

 

 

      CP_TDS_N_2D_HIST1_TYPE

 

 

 

      CP_TDS_N_2D_HIST1_X_AXIS

 

 

 

      CP_TDS_N_2D_HIST1_Y_AXIS

 

 

 

      CP_TDS_N_2D_HIST2_TYPE

 

 

 

      CP_TDS_N_2D_HIST2_X_AXIS

 

 

 

      CP_TDS_N_2D_HIST2_Y_AXIS

 

 

 

SY_TDS_N_STAT_PAR_THRESHOLD

 

 

 

      CP_TDS_ALGO_SELECTION

 

 

 

      SY_TDS_ALGO_DUST_NUM

 

 

 

      SY_TDS_ALGO_MIN_QUALITY

 

 

 

      SY_TDS_ALGO_CHANNEL

 

 

 

      SY_TDS_ALGO_STAT_ADC4

 

 

 

      SY_TDS_ALGO_STAT_ADC3

 

 

 

      SY_TDS_ALGO_STAT_ADC2

 

 

 

      SY_TDS_ALGO_STAT_ADC1

 

 

 

      SY_TDS_ALGO_MIN_AMP

 

 

 

      SY_TDS_ALGO_THRESH_WAVE

 

 

 

      SY_TDS_ALGO_THRESH_DUST

 

 

 

      SY_TDS_ALGO_THRESH_EX

 

 

 

      SY_TDS_ALGO_PARAM1

 

 

 

      SY_TDS_ALGO_PARAM2

 

 

 

TC_TDS_LOAD_NORMAL_PAR

 

 

 

SY_TDS_N_SAMP_RATE_RESERVED

 

 

 

      CP_TDS_N_SAMP_RATE

 

 

 

      SY_TDS_N_RS_RESERVED

 

 

 

      SY_TDS_N_RS_ENAB

 

 

 

      CP_TDS_N_RS_ADC_CH_NR

 

 

 

      SY_TDS_N_RS_ADC_CH4

 

 

 

      SY_TDS_N_RS_ADC_CH3

 

 

 

CP_TDS_N_1D_HIST1_AXIS

 

 

 

      CP_TDS_N_1D_HIST2_TYPE

 

 

 

      CP_TDS_N_1D_HIST2_AXIS

 

 

 

      CP_TDS_N_1D_HIST3_TYPE

 

 

 

      CP_TDS_N_1D_HIST3_AXIS

 

 

 

      CP_TDS_N_1D_HIST4_TYPE

 

 

 

      CP_TDS_N_1D_HIST4_AXIS

 

 

 

      CP_TDS_N_2D_HIST1_TYPE

 

 

 

      CP_TDS_N_2D_HIST1_X_AXIS

 

 

 

      CP_TDS_N_2D_HIST1_Y_AXIS

 

 

 

      CP_TDS_N_2D_HIST2_TYPE

 

 

 

      CP_TDS_N_2D_HIST2_X_AXIS

 

 

 

      CP_TDS_N_2D_HIST2_Y_AXIS

 

 

 

SY_TDS_N_STAT_PAR_THRESHOLD

 

 

 

      CP_TDS_ALGO_SELECTION

 

 

 

      SY_TDS_ALGO_DUST_NUM

 

 

 

      SY_TDS_ALGO_MIN_QUALITY

 

 

 

      SY_TDS_ALGO_CHANNEL

 

 

 

      SY_TDS_ALGO_STAT_ADC4

 

 

 

      SY_TDS_ALGO_STAT_ADC3

 

 

 

      SY_TDS_ALGO_STAT_ADC2

 

 

 

      SY_TDS_ALGO_STAT_ADC1

 

 

 

      SY_TDS_ALGO_MIN_AMP

 

 

 

      SY_TDS_ALGO_THRESH_WAVE

 

 

 

      SY_TDS_ALGO_THRESH_DUST

 

 

 

      SY_TDS_ALGO_THRESH_EX

 

 

 

      SY_TDS_ALGO_PARAM1

 

 

 

      SY_TDS_ALGO_PARAM2

 

 

LFR

 

LFR_LOAD_COMMON_PAR

value

TC_LFR_LOAD_NORMAL_PAR

value

 

 

 

 

SY_LFR_BW

 

      SY_LFR_N_SWF_L

 

SY_LFR_SP0

 

      SY_LFR_N_SWF_P

 

SY_LFR_SP1

 

      SY_LFR_N_ASM_P

 

SY_LFR_R0

 

      SY_LFR_N_BP_P0

 

SY_LFR_R1

 

      SY_LFR_N_BP_P1

 

SY_LFR_R2

 

      SY_LFR_N_CWF_LONG_F3

 

 

 

      PA_RPW_SPARE8_1

 

 

 

BIAS

 

TC_DPU_SET_BIAS_MODE

Value

     

 

      CP_BIA_SET_MODE_ENAB_SET_HV

 

      CP_BIA_SET_MODE_ENAB_HV

 

      CP_BIA_SET_MODE_ENAB_SET_MX

 

      CP_BIA_SET_MODE_SET_MX_MODE

 

  

 

    TC_DPU_SET_BIAS_RELAY

 

    

 

      CP_BIA_SET_RELAY_DIFF_GAIN

 

      CP_BIA_SET_RELAY_BIA_3

 

      CP_BIA_SET_RELAY_BIA_2

 

      CP_BIA_SET_RELAY_BIA_1"

 

      CP_BIA_SET_RELAY_DIFF_PROBE

 

      CP_BIA_SET_RELAY_SWITCH_P3

 

      CP_BIA_SET_RELAY_SWITCH_P2

 

      CP_BIA_SET_RELAY_SWITCH_P1

 

   

 

    TC_DPU_SET_BIAS1

 

    

 

      CP_BIA_SET_BIAS1

 

   

 

    TC_DPU_SET_BIAS2

 

   

 

    CP_BIA_SET_BIAS2

 

   

 

    TC_DPU_SET_BIAS3

 

   

 

    CP_BIA_SET_BIAS3

 

 

ROC

  • ESA will control the deployment of the iboom
  • Any TM to check?

 

 

ROLLS modes direction finding ad alta frequenza: 3 antenne entrambi monopolo e dipole. Da vedere da 10 khz verificare per TDS e LFR cosa fare.


Orbitography

TBD

Operation Constraints

At SOLO level

TBD

At RPW level

TBD

Command/Control

Give here the list of flight procedures and PDOR (TBC) required to execute this operation

Expected products

Reviews & reports

TBD

Data analysis

Expected data products

Give here the list of expected data products and their content.

Results

Give here the results of the data analysis (can be attached file, or link to references)

Meeting Notes

Actions Items

Key Summary T Created Updated Due Assignee Reporter P Status Resolution
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Attached Files

SOL-ESC-ME-10016, i1,r1 [Management of MAG and RPW data gathering during IBoom and RPW-ANT]_signed.pdf – The SSMM will finally available during these operations.

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